The overall objective of this research work is the improvement of the failure behavior of Printed Circuit Boards (PCBs). During the thermal loading of PCBs stresses arise due to the different coefficients of thermal expansion of the materials. As the current paths are made of copper, the focus is on the characterization of thin copper layers used for PCBs. The mechanical properties of these copper layers are determined in cyclic four point bending tests and in cyclic tensile-compression tests, as their behavior under changing tensile and compression loads needs to be evaluated. Specimens for the four point bend tests are manufactured by bonding 18 µm thick copper layers on both sides of 10 mm thick silicone plates. The silicone is characterized in tensile, shear and blow-up tests to provide input data for a hyperelastic material model. Specimens for the cyclic tensile-compression tests are produced in a compression molding process. Four layers of glass fiber reinforced epoxy resin and five layers of copper are applied. The results show that, due to the hyperelastic material behavior of silicone, the four point bend tests are applicable only for small strains, while the cyclic tension-compression tests can be applied to characterize thin copper foils in tension and compression up to one percent strain. Therefore such tests are conducted at different temperatures and loading conditions.
Second, cyclic material parameters are determined. The obtained material response is modeled using the “Nonlinear isotropic/kinematic hardening model” built in in the Finite Element Analysis (FEA)-software Abaqus. It is capable of modelling the cyclic plastic material behavior of metals. For every loading case the optimal set of parameters is determined using an optimization procedure. Based on the known parameter sets of the individual loading cases the calibration of a “Nonlinear isotropic/kinematic hardening model” for all R-ratios and temperatures is undertaken and the findings are discussed. The kinematic hardening parameters are fitted in an optimization process from the hysteretic force-strain curves obtained in the cyclic tension-compression tests. The isotropic hardening variables are determined based on the yield stress versus plastic strain relationship that is constructed incrementally from the available individual cycles. The so-obtained curve is found to be not unique. Hence different approaches for strain range memorization are evaluated. Since these approaches have been developed for modelling strain-controlled tests, whereas the experimental data is obtained in a force-controlled way, a phenomenological formulation is developed and applied. This model accounts for the observed mean stress dependency of the plastic properties and is thus called “mean backstress memorization model”. The results of curvature measurements during thermal cycling are used for model validation. The experimental results and the numerical predictions are in good agreement.
In the last part of this thesis, different PCB designs are tested in Interconnection Stress Tests (IST). In such tests, PCBs are subjected to temperature cycles alternating between two extremes (e.g. -40°C to 160°C). The electrical resistance is measured on-line during these tests. If the resistance rises by more than 10% of the initial value at the highest temperature, the test is terminated. The stress/strain states computed by Abaqus serve as input to a pore growth model which eventually allows working out an indicator for the electrical performance loss. Subsequently, electrical FEA are conducted to obtain a correlation between the pore volume fraction distributed over the structure and the electrical resistance increase. The results of the simulations are compared to experimental results to determine parameters. Finally the so-computed distribution of the pore volume fraction is compared to micrographs of PCBs tested in ISTs. They are in good agreement.