Simulation des "Single Via Thermal Cycle Test" - Modellerstellung und Bestimmung der Materialeingangsparameter
Research output: Thesis › Master's Thesis
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Abstract
This master thesis deals with the simulation of the "Single Via Thermal Cycle Test" (SVTCT). It was performed in cooperation with the Austria Technologie & Systemtechnik (AT&S) Aktiengesellschaft, Leoben, Austria. The “Single Via Thermal Cycle Test” is a thermal shock test, which is used to evaluate the life time of printed circuit boards under thermal loading conditions. During these tests, the vias of the tested printed circuit board are individually monitored by resistance measurements. If an increase of the electrical resistance is recorded, the conductive con-nection is broken and the end of product life is indicated. In order to conduct a finite element simulation of the SVTCT, in a first step the material input parameters were determined. The heat capacity was measured using differential scanning calorimetry and the density was determined using Archimedes’ principle. The linear thermal expansion coefficients were measured using thermomechanical analysis and digital image correlation. The mechanical properties were observed in dynamic mechanical analysis and in tensile tests. The determined properties, except for the density, were characterized temperature-dependent. The thermal expansion coefficients and the mechanical properties were determined direction-dependent. In the second part of this thesis, an axisymmetric simulation model of a single via in a printed circuit board was generated. The simulations were carried out decoupled, a model for calculating the temperature field and another model to calculate the stress and strain distribution were applied. In order to verify the thermal expansion, the linear thermal expansion coefficients of printed circuit boards in the area of a via were determined by thermomechanical analysis and also compared with the corresponding simulation results. Additionally, the calculated stress distribution was compared to microsections of vias in printed circuit boards, which had been tested in the SVTCT. All cracks occurred at locations, at which high stresses had been predicted in the simulation.
Details
Translated title of the contribution | Simulation of the "Single Via Thermal Cycle Test" - modelling and determination of the material input parameters |
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Original language | German |
Qualification | Dipl.-Ing. |
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Award date | 29 Jun 2012 |
Publication status | Published - 2012 |