High reliability is a crucial topic in the semiconductor industry. The main trend for power devices pushes toward higher current density and smaller component size. Additionally, increasing reliability and lifetime are expected. Discrete power devices are known to fail due to a number of mechanisms, such as corrosion, electromigration or stress migration and thermal expansion. All these failure mechanisms can result in various failure modes, such as chip crack, metalization layer crack or wirebond liftoff. One of the major failure mechanisms is triggered by the difference in thermal expansion of the material of the package. The thermal expansion can range from 3×10−6K−1 to 50×10−6K−1 depending whether the silicon or the mold compound are considered. Thermal cycling of these devices results in cyclic stresses in the materials. Under repetitive stress, fatigue of the material occurs. This work deals with the material behavior of a very thin die-attach alloy as well as its fatigue degradation under thermal cycling. The problem is tackled from two sides, experiment and simulation. First a material model for the studied material is obtained. A methodology to derive the elastoplastic behavior of thin films under thermal cycling is presented. This approach utilizes wafer curvature characterization techniques and finite element simulations. The material behavior is modeled with continuum plasticity. In order to determine the material parameters, Monte Carlo simulations are performed. The validity of the parameter set is assessed by comparing stress-temperature measurements with the simulated results. An adequate choice of the boundary conditions allows keeping the Finite Element model small, which reduces the computational time required due to non-linearity and multiple thermal cycle simulations. In a second step, the degradation of the layer in-situ, i.e. in the package under temperature cycling is monitored, by alternately cycling the device and regularly investigating the degradation using Scanning Acoustic Microscopy. This non-destructive technique allows to monitor crack propagation in the layer. The exact failure mode is then identified by package cross-sectioning. The failure is observed to propagate in two ways, either by interfacial delamination or by inlayer crack formation. The delamination is found to progress as a power law of the number of cycles. From the simulation point of view, the influence of parameters such as package geometry and material properties is investigated by using Linear Elastic Fracture Mechanics. A two-dimensional model of the package is built, where the materials are assumed to behave elastically and the structure is simplified by considering only the leadframe, the chip and the mold compound. Finite Element simulations yield the displacement and stress fields from which the energy release rate is calculated. Its evolution for various crack lengths is studied. It is found that the energy release rate reaches a maximum for a given combination of chip and leadframe thickness. A second simulation approach is used where the actual damage evolution is calculated. A more sophisticated model of the structure, encompassing the multiple backside layers usually present at the back of the semiconductor chip is simulated. The delamination is modeled using a cohesive zone approach. Temperature cycling and plasticity of the backside metalization layers are taken into account in the simulation. The crack propagation is shown to follow the same trend as observed in the experiment, i.e. delamination growing from the edges propagates toward the center and the crack length is a power law of the number of cycles. It has been shown that the cohesive zone approach is an appropriate technique to model degradation of the thin layers of the package under cyclic thermal loading conditions.