A Sequential Finite Volume Method / Finite Element Analysis of a Power Electronic Semiconductor Chip
Research output: Contribution to conference › Paper › peer-review
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2019. 1509-1514 Paper presented at 69th IEEE Electronic Components and Technology Conference, ECTC 2019, Las Vegas, United States.
Research output: Contribution to conference › Paper › peer-review
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T1 - A Sequential Finite Volume Method / Finite Element Analysis of a Power Electronic Semiconductor Chip
AU - Gschwandl, Mario
AU - Fuchs, P.F.
AU - Antretter, Thomas
AU - Pfost, Martin
AU - Mitev, I.
AU - Tao, Qi
AU - Krivec, Thomas
AU - Schingale, Angelika
AU - Decker, Michael
PY - 2019
Y1 - 2019
N2 - The shift of the automotive industry towards e-mobility results in a strong demand for highly reliable power electronics. A major goal in their design is to improve the thermal management of all components. Most commonly power electronics are subject to high temperature loads, either internally generated by an active part (semiconductor) or externally applied. Depending on the materials used, such as metals, polymers, etc., thermo-mechanical stresses will arise and promote different failure mechanisms. The complexity of the loading situation, especially in the case of internally generated loads, calls for a sequential approach, consisting of a Finite Volume Method (FVM) and a Finite Element Analysis (FEA) for the lifetime assessment of these components. Using this methodology, the highly complex temperature distribution of any power package can be determined. Consequently, accurate results for the thermo-mechanical stress situation from chip to power packages are deduced and critical spots are identified. Based on the obtained stress fields, an enhanced lifetime assessment of power packages can be performed. The proposed methodology is validated on a standard TO-263 package for a short circuit loading scenario.
AB - The shift of the automotive industry towards e-mobility results in a strong demand for highly reliable power electronics. A major goal in their design is to improve the thermal management of all components. Most commonly power electronics are subject to high temperature loads, either internally generated by an active part (semiconductor) or externally applied. Depending on the materials used, such as metals, polymers, etc., thermo-mechanical stresses will arise and promote different failure mechanisms. The complexity of the loading situation, especially in the case of internally generated loads, calls for a sequential approach, consisting of a Finite Volume Method (FVM) and a Finite Element Analysis (FEA) for the lifetime assessment of these components. Using this methodology, the highly complex temperature distribution of any power package can be determined. Consequently, accurate results for the thermo-mechanical stress situation from chip to power packages are deduced and critical spots are identified. Based on the obtained stress fields, an enhanced lifetime assessment of power packages can be performed. The proposed methodology is validated on a standard TO-263 package for a short circuit loading scenario.
KW - power electronics
KW - finite volume method
KW - electro-thermo-mechanical simulation
KW - Finite element analysis
U2 - 10.1109/ECTC.2019.00232
DO - 10.1109/ECTC.2019.00232
M3 - Paper
SP - 1509
EP - 1514
T2 - 69th IEEE Electronic Components and Technology Conference, ECTC 2019
Y2 - 28 May 2019 through 31 May 2019
ER -
